用于高速网络互连的多处理器体系结构

IEEE INFOCOM '89, Proceedings of the Eighth Annual Joint Conference of the IEEE Computer and Communications Societies Pub Date : 1989-04-23 DOI:10.1109/INFCOM.1989.101456

M. Zitterbart

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引用次数: 15

摘要

提出了一种适合高速网关实现的多处理器体系结构。它基于通信系统的水平和垂直细分。最终的体系结构由几个接收和发送管道组成，其中每个接收和发送管道都与连接到网关的一个子网相关联。流水线阶段是在几个处理器上实现的，这些处理器被组合成一个处理器单元。每个处理器单元的内部结构都适应于要在其上实现的协议功能。该体系结构包括管道结构和数组结构，因此允许时间并行和空间并行。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A multiprocessor architecture for high speed network interconnections

A multiprocessor architecture suitable for the implementation of high-speed gateways is presented. It is based on a horizontal and vertical subdivision of communication systems. The resulting architecture consists of several receive and send pipelines, where every receive and send pipeline is associated with one subnetwork connected to the gateway. The pipeline stages are implemented on several processors which are combined into a processor unit. The internal structure of each processor unit is adapted to the protocol functions that are to be implemented on it. The architecture comprises pipeline structures and array structures and thus permits temporal parallelism as well as spatial parallelism.<>

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IEEE INFOCOM '89, Proceedings of the Eighth Annual Joint Conference of the IEEE Computer and Communications Societies

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