{"title":"先进的CMOS采用哪个结?-理论、基准和预测","authors":"T. Skotnicki","doi":"10.1109/IWJT.2005.203865","DOIUrl":null,"url":null,"abstract":"In this paper, the theoretical considerations about junction design for advanced CMOS, to benchmark the most recent and advanced results, and make some predictions on the future needs are presented. Junction scaling is the key difference that grants better electrostatic integrity (essentially smaller DIBL) to SON/SOI and DG structures if compared with bulk. With the use of these structures, DIBL can be kept under control (<100 mV) down to 5-10 nm gate length.","PeriodicalId":307038,"journal":{"name":"Extended Abstracts of the Fifth International Workshop on Junction Technology","volume":"7 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Which junction for advanced CMOS?-theory, benchmark and predictions\",\"authors\":\"T. Skotnicki\",\"doi\":\"10.1109/IWJT.2005.203865\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, the theoretical considerations about junction design for advanced CMOS, to benchmark the most recent and advanced results, and make some predictions on the future needs are presented. Junction scaling is the key difference that grants better electrostatic integrity (essentially smaller DIBL) to SON/SOI and DG structures if compared with bulk. With the use of these structures, DIBL can be kept under control (<100 mV) down to 5-10 nm gate length.\",\"PeriodicalId\":307038,\"journal\":{\"name\":\"Extended Abstracts of the Fifth International Workshop on Junction Technology\",\"volume\":\"7 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2005-06-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Extended Abstracts of the Fifth International Workshop on Junction Technology\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IWJT.2005.203865\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Extended Abstracts of the Fifth International Workshop on Junction Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IWJT.2005.203865","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Which junction for advanced CMOS?-theory, benchmark and predictions
In this paper, the theoretical considerations about junction design for advanced CMOS, to benchmark the most recent and advanced results, and make some predictions on the future needs are presented. Junction scaling is the key difference that grants better electrostatic integrity (essentially smaller DIBL) to SON/SOI and DG structures if compared with bulk. With the use of these structures, DIBL can be kept under control (<100 mV) down to 5-10 nm gate length.
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