VLSI测试系统中高速复用器与解复用器集成的若干问题

Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's Pub Date : 1991-04-15 DOI:10.1109/VTEST.1991.208142

M. Chowanetz, C. Kuntzsch, W. Wolz

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引用次数: 0

摘要

介绍了高速测试通道设计的硬件和软件解决方案。采用砷化镓电路合并测试引脚波形，实现了小于1ns的周期。讨论了硬件设计方案，并介绍了一种自动生成测试人员可读模式描述文件的方案。本文描述了允许这种生成的转换算法。

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Aspects on integration of high-speed multiplexers and demultiplexers in VLSI test systems

The authors describe hardware and software solutions for the design of a high-speed tester channel. Using gallium-arsenide circuitry for the merging of tester pin waveforms, cycle periods of less than 1 ns have been achieved. Hardware design alternatives are discussed, and a scheme for the automatic generation of tester-readable pattern description files is introduced. The conversion algorithms that allow for this generation are described.<>

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Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's

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