Analysis and modeling of drift-resilient time-based integrated resistive sensor interfaces

This paper presents the drift analysis and improvement of integrated resistive sensor interfaces, focusing on BBPLL-based architectures. This architecture is intrinsically resilient to drift generated by environmental and circuit degradation effects due to its time-domain and highly-digital implementation. Nevertheless, for applications aiming at nearly zero drift, non-ideal effects resulting from mismatch and nonlinearity are still creating residual drift. Two proposed feedback mechanisms are studied under non-ideal circuit conditions. System-level analysis and simulations predict the remaining output error when the main non-ideal effects produced by environmental changes and circuit degradation occur. The chopping technique is included in the analysis as a drift-compensation mechanism. This technique fits well with a single-ended bridge to effectively remove drift effects. The results show that the drift error due to mismatch is attenuated within ±0.05% of the full scale, corresponding to a 10X improvement with respect to previous publications.