Low-complexity CORDIC-based VLSI design and FPGA prototype of CI-OFDMA system for next-generation

Carrier Interferometry orthogonal frequency division multiple access (CI-OFDMA) is an attractive choice for next-generation wireless communication and is considered as an alternative to OFDM with low peak-to-average-power-ratio (PAPR) and inter-carrier-symbol interference (ISI). The implementation of the real-time multicarrier communication system is restricted by the huge hardware cost and the complexity associated with a large number of computations. In this paper, a low-complexity real-time co-ordinate rotational digital computer (CORDIC)-based very-large scale integration (VLSI) architecture is proposed for CI-OFDMA system. To date, there is no field programmable gate array (FPGA) prototype that is addressed for the CORDIC-based real-time CI-OFDMA wireless system. In this context, we have proposed a new hardware-efficient and flexible CORDIC-based CI-OFDMA architecture. The novelty of this proposed architecture is its capability of changing the number of orthogonal subcarriers and user symbols upto the maximum 32K for the 16-bit word size architecture that is suitable for most of the current and upcoming wireless standards. The architecture is prototyped using commercially available FPGA device XC3S500E-5FG320. The implementation and experimental results of this proposed scheme are highlighted and validated with the result obtained by MATLAB simulation.