{"title":"高性能流水线ADC中功率可缩放的MD AC设计","authors":"Fei Pei, Honghui Deng, Yongsheng Yin","doi":"10.1109/ICASID.2010.5551522","DOIUrl":null,"url":null,"abstract":"A 9-bit, 125MSPS, power scaleable MDAC applied in high performance pipelined ADC in 1.8V supply voltage, 0.18um CMOS process is presented in this paper. The related circuits: a high gain, high unit gain bandwidth operational amplifier with gain boosting, common-mode feedback and bootstrap are proposed. Additionally, when the sampling rate is changed, the power of the whole MDAC can be significantly modulated by setting modulations of bias in op amp with different combinations of current sources. Simulation results in a 0.18um CMOS process indicated that when programmed at 125MSPS, the signal can correctly set up in 2.1ns; MDAC exhibits a spurious free dynamic range (SFDR)of 73.1 dB and a signal-to-noise and distortion ratio(SNDR)of 60.23dB. It consumes 6.8mw when a 62MHz sine signal is fed in.1","PeriodicalId":391931,"journal":{"name":"2010 International Conference on Anti-Counterfeiting, Security and Identification","volume":"19 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Design of power scaleable MD AC in high performance pipelined ADC\",\"authors\":\"Fei Pei, Honghui Deng, Yongsheng Yin\",\"doi\":\"10.1109/ICASID.2010.5551522\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 9-bit, 125MSPS, power scaleable MDAC applied in high performance pipelined ADC in 1.8V supply voltage, 0.18um CMOS process is presented in this paper. The related circuits: a high gain, high unit gain bandwidth operational amplifier with gain boosting, common-mode feedback and bootstrap are proposed. Additionally, when the sampling rate is changed, the power of the whole MDAC can be significantly modulated by setting modulations of bias in op amp with different combinations of current sources. Simulation results in a 0.18um CMOS process indicated that when programmed at 125MSPS, the signal can correctly set up in 2.1ns; MDAC exhibits a spurious free dynamic range (SFDR)of 73.1 dB and a signal-to-noise and distortion ratio(SNDR)of 60.23dB. It consumes 6.8mw when a 62MHz sine signal is fed in.1\",\"PeriodicalId\":391931,\"journal\":{\"name\":\"2010 International Conference on Anti-Counterfeiting, Security and Identification\",\"volume\":\"19 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-07-18\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2010 International Conference on Anti-Counterfeiting, Security and Identification\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICASID.2010.5551522\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 International Conference on Anti-Counterfeiting, Security and Identification","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICASID.2010.5551522","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design of power scaleable MD AC in high performance pipelined ADC
A 9-bit, 125MSPS, power scaleable MDAC applied in high performance pipelined ADC in 1.8V supply voltage, 0.18um CMOS process is presented in this paper. The related circuits: a high gain, high unit gain bandwidth operational amplifier with gain boosting, common-mode feedback and bootstrap are proposed. Additionally, when the sampling rate is changed, the power of the whole MDAC can be significantly modulated by setting modulations of bias in op amp with different combinations of current sources. Simulation results in a 0.18um CMOS process indicated that when programmed at 125MSPS, the signal can correctly set up in 2.1ns; MDAC exhibits a spurious free dynamic range (SFDR)of 73.1 dB and a signal-to-noise and distortion ratio(SNDR)of 60.23dB. It consumes 6.8mw when a 62MHz sine signal is fed in.1
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