{"title":"超低功耗亚阈值环形振荡器的自级联体偏置技术","authors":"K. Reddy, P. Rao","doi":"10.1109/ICITIIT54346.2022.9744168","DOIUrl":null,"url":null,"abstract":"The paper presents a low-power sub-threshold ring oscillator for self-powered IoT devices.Self cascoded body biasing technique is applied to each inverter in ring oscillator to enable low voltage operation. As a result, higher body biasing magnitudes are achieved compared to the conventional body biasing scheme. Furthermore, a significant reduction in subthreshold-leakage current accordingly reduces the power consumption. A three-stage ring oscillator circuit is designed for the desired oscillating frequency of 2.65 MHz. The proposed design has been implemented in standard CMOS 180 nm technology. Post-layout simulation results describe the proposed design takes low power consumption of 58.9 nW at the minimum supply voltage of 270 mV.","PeriodicalId":184353,"journal":{"name":"2022 International Conference on Innovative Trends in Information Technology (ICITIIT)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-02-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A Self cascoded body biasing technique for ultra-low-power sub-threshold ring oscillator\",\"authors\":\"K. Reddy, P. Rao\",\"doi\":\"10.1109/ICITIIT54346.2022.9744168\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The paper presents a low-power sub-threshold ring oscillator for self-powered IoT devices.Self cascoded body biasing technique is applied to each inverter in ring oscillator to enable low voltage operation. As a result, higher body biasing magnitudes are achieved compared to the conventional body biasing scheme. Furthermore, a significant reduction in subthreshold-leakage current accordingly reduces the power consumption. A three-stage ring oscillator circuit is designed for the desired oscillating frequency of 2.65 MHz. The proposed design has been implemented in standard CMOS 180 nm technology. Post-layout simulation results describe the proposed design takes low power consumption of 58.9 nW at the minimum supply voltage of 270 mV.\",\"PeriodicalId\":184353,\"journal\":{\"name\":\"2022 International Conference on Innovative Trends in Information Technology (ICITIIT)\",\"volume\":\"52 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2022-02-12\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2022 International Conference on Innovative Trends in Information Technology (ICITIIT)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICITIIT54346.2022.9744168\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 International Conference on Innovative Trends in Information Technology (ICITIIT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICITIIT54346.2022.9744168","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A Self cascoded body biasing technique for ultra-low-power sub-threshold ring oscillator
The paper presents a low-power sub-threshold ring oscillator for self-powered IoT devices.Self cascoded body biasing technique is applied to each inverter in ring oscillator to enable low voltage operation. As a result, higher body biasing magnitudes are achieved compared to the conventional body biasing scheme. Furthermore, a significant reduction in subthreshold-leakage current accordingly reduces the power consumption. A three-stage ring oscillator circuit is designed for the desired oscillating frequency of 2.65 MHz. The proposed design has been implemented in standard CMOS 180 nm technology. Post-layout simulation results describe the proposed design takes low power consumption of 58.9 nW at the minimum supply voltage of 270 mV.