利用等离子体辅助掺杂在三维器件结构上形成超浅结

Y. S. Kim, YounGi Hong, I. Berry
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引用次数: 1

摘要

先进的电感耦合等离子体技术和表面处理已经在低能量下证明了5nm共形浅结,没有硅结构损伤。随着晶片温度的升高,n型PH3等离子体辅助掺杂的特点是掺杂物扩散和电活化。等离子体辅助掺杂在高晶圆温度下,即使在高入射能量条件下施加偏置功率,也没有对晶圆结构造成损伤,而在低入射能量条件下,在不施加偏置功率的情况下,可以形成小于7nm的Xj形成的浅结。在PH3掺杂前,在去耦等离子体条件下加入硅表面修饰步骤,可以显著提高掺杂水平,降低Rs。我们比较了不同的退火技术,以了解对形成小于7nm的浅结的掺杂激活和水平的影响。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Ultra shallow junction (USJ) formation using plasma assisted doping on 3D devices structures
Advanced inductively coupled plasma techniques and surface treatments have been used to demonstrate 5nm conformal shallow junctions at low energy with no silicon structure damage. N-type PH3 plasma assisted doping was characterized by dopant diffusion and electrical activation with increasing wafer temperature. Plasma assisted doping at high wafer temperature showed no structure damage even at a high incident energy condition with a bias power applied to the wafer, while a shallow junction of less than 7nm of Xj formation was achieved with low incident energy condition without bias power. Adding a silicon surface modification step when using the decoupled plasma condition prior to PH3 doping was found to enhance the dopant level and lower Rs dramatically. Various annealing techniques were compared to understand the impact to dopant activation and levels to form shallow junctions of less than 7nm.
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