基于标准BCD工艺的电源管理芯片欠压闭锁电路优化设计

2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM) Pub Date : 2017-11-01 DOI:10.1109/ICAM.2017.8242143

Shulin Liu, Qianqian Wang, Chaoying Wang, Zhi Huang

{"title":"基于标准BCD工艺的电源管理芯片欠压闭锁电路优化设计","authors":"Shulin Liu, Qianqian Wang, Chaoying Wang, Zhi Huang","doi":"10.1109/ICAM.2017.8242143","DOIUrl":null,"url":null,"abstract":"An optimization design of an Under Voltage Lockout (UVLO) circuit in a bipolar CMOS DMOS (BCD) process is presented in this paper. Compared with the traditional structure, the proposed circuit effectively reduces the hysteresis voltage drift with temperature by introducing the high-order temperature compensation function to the band-gap reference. Thus, the reliability of the UVLO circuit is improved. The designed UVLO circuit has an input high threshold voltage of 8.2 V, low threshold voltage of 5.6 V and a hysteresis range of 2.6 V when T = 25C. The maximum deviation is 0.3V within −30 ∼ 140C. In a standard BCD process, the designed circuit is simulated by using Spectre in Cadence. The feasibility and correctness of the designed UVLO circuit is proven by the simulation results.","PeriodicalId":117801,"journal":{"name":"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Optimization design of under voltage lockout circuit in power management chips based on standard BCD process\",\"authors\":\"Shulin Liu, Qianqian Wang, Chaoying Wang, Zhi Huang\",\"doi\":\"10.1109/ICAM.2017.8242143\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An optimization design of an Under Voltage Lockout (UVLO) circuit in a bipolar CMOS DMOS (BCD) process is presented in this paper. Compared with the traditional structure, the proposed circuit effectively reduces the hysteresis voltage drift with temperature by introducing the high-order temperature compensation function to the band-gap reference. Thus, the reliability of the UVLO circuit is improved. The designed UVLO circuit has an input high threshold voltage of 8.2 V, low threshold voltage of 5.6 V and a hysteresis range of 2.6 V when T = 25C. The maximum deviation is 0.3V within −30 ∼ 140C. In a standard BCD process, the designed circuit is simulated by using Spectre in Cadence. The feasibility and correctness of the designed UVLO circuit is proven by the simulation results.\",\"PeriodicalId\":117801,\"journal\":{\"name\":\"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)\",\"volume\":\"13 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICAM.2017.8242143\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICAM.2017.8242143","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 2

摘要

提出了一种双极CMOS DMOS (BCD)工艺中欠压锁相电路的优化设计。与传统结构相比，该电路通过在带隙基准中引入高阶温度补偿函数，有效地降低了滞后电压随温度的漂移。从而提高了UVLO电路的可靠性。所设计的UVLO电路在T = 25C时的输入高阈值电压为8.2 V，低阈值电压为5.6 V，滞回范围为2.6 V。在−30 ~ 140C范围内最大偏差为0.3V。在标准的BCD过程中，使用Spectre在Cadence中对设计的电路进行了仿真。仿真结果验证了所设计UVLO电路的可行性和正确性。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

Optimization design of under voltage lockout circuit in power management chips based on standard BCD process

An optimization design of an Under Voltage Lockout (UVLO) circuit in a bipolar CMOS DMOS (BCD) process is presented in this paper. Compared with the traditional structure, the proposed circuit effectively reduces the hysteresis voltage drift with temperature by introducing the high-order temperature compensation function to the band-gap reference. Thus, the reliability of the UVLO circuit is improved. The designed UVLO circuit has an input high threshold voltage of 8.2 V, low threshold voltage of 5.6 V and a hysteresis range of 2.6 V when T = 25C. The maximum deviation is 0.3V within −30 ∼ 140C. In a standard BCD process, the designed circuit is simulated by using Spectre in Cadence. The feasibility and correctness of the designed UVLO circuit is proven by the simulation results.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)

自引率

0.00%

发文量