{"title":"用于SoC网络处理平台的高速系统总线","authors":"J.P. Bissou, M. Dubois, Y. Savaria, G. Bois","doi":"10.1109/ICM.2003.238564","DOIUrl":null,"url":null,"abstract":"Interconnecting modules in a SoC platform requires modules compatibility. Several solutions are available, but they either lack the necessary throughput or the flexibility. This paper proposes an interconnection architecture for a flexible on-chip high-performance communication medium that can provide variable bandwidth. It is based on the AHB AMBA bus. The proposed architecture has been implemented in the Seamless environment and laid out using a 0.18 /spl mu/m CMOS with Cadence tools to validate the proposed concept.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"88 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"High-speed system bus for a SoC network processing platform\",\"authors\":\"J.P. Bissou, M. Dubois, Y. Savaria, G. Bois\",\"doi\":\"10.1109/ICM.2003.238564\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Interconnecting modules in a SoC platform requires modules compatibility. Several solutions are available, but they either lack the necessary throughput or the flexibility. This paper proposes an interconnection architecture for a flexible on-chip high-performance communication medium that can provide variable bandwidth. It is based on the AHB AMBA bus. The proposed architecture has been implemented in the Seamless environment and laid out using a 0.18 /spl mu/m CMOS with Cadence tools to validate the proposed concept.\",\"PeriodicalId\":180690,\"journal\":{\"name\":\"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)\",\"volume\":\"88 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICM.2003.238564\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICM.2003.238564","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
High-speed system bus for a SoC network processing platform
Interconnecting modules in a SoC platform requires modules compatibility. Several solutions are available, but they either lack the necessary throughput or the flexibility. This paper proposes an interconnection architecture for a flexible on-chip high-performance communication medium that can provide variable bandwidth. It is based on the AHB AMBA bus. The proposed architecture has been implemented in the Seamless environment and laid out using a 0.18 /spl mu/m CMOS with Cadence tools to validate the proposed concept.