J. Demarest, N. Arnold, K. Brew, V. Chan, A. Cote, T. Gordon, M. Iwatake, G. Lian, J. Li, I. Ok, S. Mcdermott, I. Saraf, N. Saulnier, L. Tierney, A. Varghese
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Failure Analysis Challenges of Phase Change Memory Test Structures with Two Case Studies
There are several variants of artificial intelligence (AI) hardware structures which are under study by the semiconductor industry as potential future synergistic technology adders to existing complementary metal–oxide–semiconductor (CMOS) designs. This paper will discuss some of the failure analysis challenges which have appeared in discrete test structures and test arrays of an exploratory PCM program at IBM's Albany AI Hardware Research Center.
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