{"title":"一种校验算术单元制造技术","authors":"Richard A. Davis","doi":"10.1145/1463891.1463969","DOIUrl":null,"url":null,"abstract":"In conjunction with studies of mechanizations for a 30-bit digital computer arithmetic unit, an investigation of techniques for checking arithmetic unit operations was conducted. The objectives were to provide maximum protection against undetected errors, while holding the cost of checking to a minimum. In addition, no loss of arithmetic unit speed should result. Finally, the checking process should give protection against memory-unit-induced errors.","PeriodicalId":143723,"journal":{"name":"AFIPS '65 (Fall, part I)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1965-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"A checking arithmetic unit\",\"authors\":\"Richard A. Davis\",\"doi\":\"10.1145/1463891.1463969\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In conjunction with studies of mechanizations for a 30-bit digital computer arithmetic unit, an investigation of techniques for checking arithmetic unit operations was conducted. The objectives were to provide maximum protection against undetected errors, while holding the cost of checking to a minimum. In addition, no loss of arithmetic unit speed should result. Finally, the checking process should give protection against memory-unit-induced errors.\",\"PeriodicalId\":143723,\"journal\":{\"name\":\"AFIPS '65 (Fall, part I)\",\"volume\":\"65 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1965-11-30\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"AFIPS '65 (Fall, part I)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1145/1463891.1463969\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"AFIPS '65 (Fall, part I)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/1463891.1463969","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
In conjunction with studies of mechanizations for a 30-bit digital computer arithmetic unit, an investigation of techniques for checking arithmetic unit operations was conducted. The objectives were to provide maximum protection against undetected errors, while holding the cost of checking to a minimum. In addition, no loss of arithmetic unit speed should result. Finally, the checking process should give protection against memory-unit-induced errors.