FPGA中的8通道高分辨率TDC

2015 IEEE Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC) Pub Date : 2015-10-01 DOI:10.1109/NSSMIC.2015.7581245

N. Lusardi, A. Geraci

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引用次数: 16

摘要

在本文中，我们介绍了在Xilinx Kintex-7 FPGA器件中实现的8通道抽头延迟线(TDL) TDC，其rms值分辨率约为20 ps。该仪器的主要特点是节省资源和低功耗架构，存在能够在一个时钟周期内感知沿延迟线传播的过渡位置的边缘检测器，接口通过USB 3.0通信门。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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8-Channels high-resolution TDC in FPGA

In this contribution we presented the implementation of a tapped-delay-line (TDL) TDC with 8-channels in a Xilinx Kintex-7 FPGA device with r.m.s. value of the resolution around 20 ps. Main features of the instrument are the resource-saving and low-power architecture, the presence of an edge detector able to sense the position of the transition propagating along the delay line within one clock cycle, the interface through a USB 3.0 communication gate.

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2015 IEEE Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC)

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