HDP dielectric BEOL gapfill: a process for manufacturing

As BEOL spacing decreases and aspect ratios increase, conventional dielectric gap filling techniques begin to lose capability. At Digital Semiconductor two different ILD gap fill processes have been evaluated for running in production. At or below 0.5 um spacing an integrated PETEOS/SACVD PETEOS gap fill process showed great variability in providing good gap fill without the creation of voids. In our 0.35 um process an HDP oxide deposition using an ECR deposition system has now replaced the PETEOS/SACVD gap fill process. While providing process simplification in the deposition tool, tool availability, integration, yield and device testing have shown that the HDP process is equally capable while providing robust void free gap fill. The HDP ECR oxide has been integrated with a conventional PECVD TEOS oxide deposition and CMP in a 4 layer metal 0.35 um process. The integration of an HDP oxide with a high throughput PETEOS deposition tool provides manufacturing with a high throughput process. CMP provides global planarization, essential for photo depth of field and integration with tungsten plug formation.