Transistor Sizing Scheme for DICE-Based Radiation-Resilient Latches

Recently, radiation-aware latch designs have been increasingly important due to the aggressive VLSI scaling. From radiation, latched data can be flipped due to single event upset (SEU) at a single node or multiple nodes in a circuit. Therefore, we need to develop SEU-resilient latches. DICE-based latches has remarkable features during SEU recovery. To our knowledge, there is no systematic analysis of transistor sizes for the DICE-based latch designs. In this paper, we propose transistor sizing scheme for radiation-resilient latches to single node upset and multiple node upsets.