A Low Power Reference Voltage Buffer and High Density Unit capacitor in a 12b 200MS/s SAR ADC

This paper introduces a low power reference voltage buffer(RVB) and a MIM-MOM combinational unit capacitor for high speed ADC. The proposed RVB adopts flipped voltage follower(FVF) technique achieving lower output impedance to reduce power consumption and a normal supply voltage can be used. The unit capacitor is a full surrounded structure, in which the top plate is enwrapped by the bottom plate to reduce the parasite capacitance on it. High density and good matching can be achieved. The concept is applied to a 12b 200MS/s SAR ADC with recombination redundancy scheme in 28 nm CMOS. The ADC and RVB consume 1.88mW and 2.4mW, respectively. The simulation shows that the SNDR and SFDR are 64.79dB and 76.71dB with a 95.3MHz input.