{"title":"POWER2: TPC-C的性能测量与分析","authors":"M. T. Franklin, Edward H. Welbon","doi":"10.1109/CMPCON.1994.282900","DOIUrl":null,"url":null,"abstract":"This paper discusses the implementation and features of the POWER2 system's embedded hardware performance monitor, describes its application to the analysis of the behavior of the Transaction Processing Performance Council's TPC-C benchmark on the POWER2 CPU, simulating an on-line transaction processing (OLTP) workload, and summarizes the results of the analysis. The POWER2 performance monitor provides hardware measures that are important to software developers tuning the operating system and application software, as well as to system designers responsible for the development of new systems. The measures characterize storage system performance and compiler instruction scheduling opportunity, both critical to good system performance.<<ETX>>","PeriodicalId":321074,"journal":{"name":"Proceedings of COMPCON '94","volume":"32 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"POWER2: performance measurement and analysis of TPC-C\",\"authors\":\"M. T. Franklin, Edward H. Welbon\",\"doi\":\"10.1109/CMPCON.1994.282900\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper discusses the implementation and features of the POWER2 system's embedded hardware performance monitor, describes its application to the analysis of the behavior of the Transaction Processing Performance Council's TPC-C benchmark on the POWER2 CPU, simulating an on-line transaction processing (OLTP) workload, and summarizes the results of the analysis. The POWER2 performance monitor provides hardware measures that are important to software developers tuning the operating system and application software, as well as to system designers responsible for the development of new systems. The measures characterize storage system performance and compiler instruction scheduling opportunity, both critical to good system performance.<<ETX>>\",\"PeriodicalId\":321074,\"journal\":{\"name\":\"Proceedings of COMPCON '94\",\"volume\":\"32 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1994-02-28\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of COMPCON '94\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CMPCON.1994.282900\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of COMPCON '94","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CMPCON.1994.282900","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
POWER2: performance measurement and analysis of TPC-C
This paper discusses the implementation and features of the POWER2 system's embedded hardware performance monitor, describes its application to the analysis of the behavior of the Transaction Processing Performance Council's TPC-C benchmark on the POWER2 CPU, simulating an on-line transaction processing (OLTP) workload, and summarizes the results of the analysis. The POWER2 performance monitor provides hardware measures that are important to software developers tuning the operating system and application software, as well as to system designers responsible for the development of new systems. The measures characterize storage system performance and compiler instruction scheduling opportunity, both critical to good system performance.<>
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