{"title":"一个0.24 mW, 14.4 kbps, r=1/2, K=9的维特比解码器","authors":"I. Kang, A. Willson","doi":"10.1109/CICC.1997.606698","DOIUrl":null,"url":null,"abstract":"An r=1/2, K=9 Viterbi decoder IC for CDMA transceivers consumes 0.24 mW at a power supply voltage of 1.65 V, a data rate of 14.4 kbps, and a clock speed of 0.9216 MHz. Its core consists of approximately 65 k transistors, occupying 1.9/spl times/3.4 mm/sup 2/ in a 0.8-/spl mu/m triple-layer-metal n-well CMOS technology.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"13 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"A 0.24 mW, 14.4 kbps, r=1/2, K=9 Viterbi decoder\",\"authors\":\"I. Kang, A. Willson\",\"doi\":\"10.1109/CICC.1997.606698\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An r=1/2, K=9 Viterbi decoder IC for CDMA transceivers consumes 0.24 mW at a power supply voltage of 1.65 V, a data rate of 14.4 kbps, and a clock speed of 0.9216 MHz. Its core consists of approximately 65 k transistors, occupying 1.9/spl times/3.4 mm/sup 2/ in a 0.8-/spl mu/m triple-layer-metal n-well CMOS technology.\",\"PeriodicalId\":111737,\"journal\":{\"name\":\"Proceedings of CICC 97 - Custom Integrated Circuits Conference\",\"volume\":\"13 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1997-05-05\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of CICC 97 - Custom Integrated Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CICC.1997.606698\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.1997.606698","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An r=1/2, K=9 Viterbi decoder IC for CDMA transceivers consumes 0.24 mW at a power supply voltage of 1.65 V, a data rate of 14.4 kbps, and a clock speed of 0.9216 MHz. Its core consists of approximately 65 k transistors, occupying 1.9/spl times/3.4 mm/sup 2/ in a 0.8-/spl mu/m triple-layer-metal n-well CMOS technology.
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