Implementation of statistical characterisation and design techniques for an industrial 0.5 /spl mu/m CMOS technology

This paper presents a methodology for statistical worst-case simulation using the BSIM3v3 model within commercially available tools. Statistical techniques such as principal component analysis and Box-Behnken designs are used to generate a subset of models which reflect the variation of measured device performance. These worst-case corners can be used in circuit simulation to account for the effects of statistical fluctuation on circuit performance. An indication of key process parameters that need to be monitored and controlled is also provided.