{"title":"基于Xilinx千兆收发器的光通信框架的开发","authors":"Vedant Chikhale, N. Wankhede, Smita S. Hande","doi":"10.1109/ICNTE44896.2019.8945995","DOIUrl":null,"url":null,"abstract":"In recent years, many FPGA vendors have come up with high speed transceiver blocks which handle all the physical layer signaling and Media Access layer operations required to achieve robust high speed communication. Also, optical communication is suitable for high bandwidth applications and gaining popularity over any other wired media which are currently used with FPGA implementations. This proposed research work is to focus on achieving optical fiber link with Xilinx Gigabit transceiver block for data rates of over 3.125 Gbps transmitted serially. The optical digital link will be established between two FPGA boards which are Spartan 6 Series SP605 boards which can be coupled to optical transceiver modules known as SFP. The basic GTP MAC wrapper core from Xilinx is being used as base for data transmission and reception. GTP performance is validated with the help of Xilinx bit error test known as IBERT. The results of the IBERT test are observed and calculated using Chip-Scope-Pro analyzer to obtain the faults in connections, defects in medium, bit error ratio and bit error detection during transmission and reception. Various ports in each GTP tile required for clock, reset, encoding, decoding, serialization, deserialization, error correction, polarity control, pattern checking, etc are used to run a code which will enable the actual transmission and reception of information bits with high data rate with very low bit error rate.","PeriodicalId":292408,"journal":{"name":"2019 International Conference on Nascent Technologies in Engineering (ICNTE)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Development of Optical Communication Framework with Xilinx Gigabit Transceivers\",\"authors\":\"Vedant Chikhale, N. Wankhede, Smita S. Hande\",\"doi\":\"10.1109/ICNTE44896.2019.8945995\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In recent years, many FPGA vendors have come up with high speed transceiver blocks which handle all the physical layer signaling and Media Access layer operations required to achieve robust high speed communication. Also, optical communication is suitable for high bandwidth applications and gaining popularity over any other wired media which are currently used with FPGA implementations. This proposed research work is to focus on achieving optical fiber link with Xilinx Gigabit transceiver block for data rates of over 3.125 Gbps transmitted serially. The optical digital link will be established between two FPGA boards which are Spartan 6 Series SP605 boards which can be coupled to optical transceiver modules known as SFP. The basic GTP MAC wrapper core from Xilinx is being used as base for data transmission and reception. GTP performance is validated with the help of Xilinx bit error test known as IBERT. The results of the IBERT test are observed and calculated using Chip-Scope-Pro analyzer to obtain the faults in connections, defects in medium, bit error ratio and bit error detection during transmission and reception. Various ports in each GTP tile required for clock, reset, encoding, decoding, serialization, deserialization, error correction, polarity control, pattern checking, etc are used to run a code which will enable the actual transmission and reception of information bits with high data rate with very low bit error rate.\",\"PeriodicalId\":292408,\"journal\":{\"name\":\"2019 International Conference on Nascent Technologies in Engineering (ICNTE)\",\"volume\":\"2 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 International Conference on Nascent Technologies in Engineering (ICNTE)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICNTE44896.2019.8945995\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 International Conference on Nascent Technologies in Engineering (ICNTE)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICNTE44896.2019.8945995","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Development of Optical Communication Framework with Xilinx Gigabit Transceivers
In recent years, many FPGA vendors have come up with high speed transceiver blocks which handle all the physical layer signaling and Media Access layer operations required to achieve robust high speed communication. Also, optical communication is suitable for high bandwidth applications and gaining popularity over any other wired media which are currently used with FPGA implementations. This proposed research work is to focus on achieving optical fiber link with Xilinx Gigabit transceiver block for data rates of over 3.125 Gbps transmitted serially. The optical digital link will be established between two FPGA boards which are Spartan 6 Series SP605 boards which can be coupled to optical transceiver modules known as SFP. The basic GTP MAC wrapper core from Xilinx is being used as base for data transmission and reception. GTP performance is validated with the help of Xilinx bit error test known as IBERT. The results of the IBERT test are observed and calculated using Chip-Scope-Pro analyzer to obtain the faults in connections, defects in medium, bit error ratio and bit error detection during transmission and reception. Various ports in each GTP tile required for clock, reset, encoding, decoding, serialization, deserialization, error correction, polarity control, pattern checking, etc are used to run a code which will enable the actual transmission and reception of information bits with high data rate with very low bit error rate.