Multi-Threshold CMOS Devices: A Comparative Analysis of Leakage Power and Delay in Digital Circuits for Nano-Scale Technology

In today’s technology trend creative and effective design solution is necessary in order to design high performance CMOS VLSI circuits. In nano-scale technology leakage power contributes a large amount of entire power dissipation of a circuit. The main cause of increased leakage power is due to process parameter decrease. Therefore, power dissipation in small devices are now a primary design challenge. Excessive power dissipation can be controlled by reducing supply voltage but that will increase propagation delay. So, we have the dilemma of power and speed in high performance circuit design. A designer must tradeoff between power and speed based on requirement. Multi-threshold CMOS can be an excellent choice to implement in a larger design to achieve most optimum circuit performance. In MTCMOS technology there are low threshold (LVT) CMOS devices & high threshold (HVT) CMOS devices. LVT CMOS can be used where high speed is required while HVT CMOS can be used for low power requirement. In some cases, an optimum design should be a combination of both HVT and LVT. In this paper four widely used D flip flop integrated circuits are taken as examples and analyzed with MTCMOS - LVT & HVT separately. Various performance parameters such as total power, leakage power, propagation delay & leakage power and delay product (PDP) are analyzed. A comparative analysis of power versus delay in four types of D flip flop topologies with MTCMOS are presented afterwards. All the designs are simulated in cadence virtuoso 45nm technology.