fpga的实际模型检查

Shenghsun Cho, Mrunal Patel, M. Ferdman, Peter Milder
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引用次数: 0

摘要

软件验证是软件开发过程的一个重要阶段,特别是对于任务关键型系统。由于使用单元测试的传统方法无法验证复杂的软件,开发人员越来越依赖于正式的验证方法,例如显式状态模型检查,来自动验证软件是否正常运行。然而,由于软件设计的复杂性不断增加,在通用内核上运行时,无法在合理的时间内执行模型检查,这导致了对硬件加速模型检查的探索。fpga已被证明是有前途的验证加速器,显示出比软件快近三个数量级的速度。不幸的是,“FPGA可编程性墙”,特别是较长的合成和放置和路由时间,阻碍了FPGA用于模型检查的普遍采用。为了解决这个问题,我们专门为fpga上的模型检查器设计了一个运行时可编程管道,以最大限度地减少模型检查前的“准备时间”。我们设计的后继状态生成器和状态验证器模块可以实现FPGA加速模型检查,而不会产生耗时的FPGA实现阶段,将模型检查前的准备时间从几个小时减少到不到一分钟,而与特定于模型的实现相比,只产生26%的执行时间开销。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Practical Model Checking on FPGAs
Software verification is an important stage of the software development process, particularly for mission-critical systems. As the traditional methodology of using unit tests falls short of verifying complex software, developers are increasingly relying on formal verification methods, such as explicit state model checking, to automatically verify that the software functions properly. However, due to the ever-increasing complexity of software designs, model checking cannot be performed in a reasonable amount of time when running on general-purpose cores, leading to the exploration of hardware-accelerated model checking. FPGAs have been demonstrated to be promising verification accelerators, exhibiting nearly three orders of magnitude speedup over software. Unfortunately, the “FPGA programmability wall,” particularly the long synthesis and place-and-route times, block the general adoption of FPGAs for model checking. To address this problem, we designed a runtime-programmable pipeline specifically for model checkers on FPGAs to minimize the “preparation time” before a model can be checked. Our design of the successor state generator and the state validator modules enables FPGA-acceleration of model checking without incurring the time-consuming FPGA implementation stages, reducing the preparation time before checking a model from hours to less than a minute, while incurring only a 26% execution time overhead compared to model-specific implementations.
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