{"title":"用于7nm Hexagon™计算DSP的电流和温度限制系统的随机脉冲调制指令发布控制电路","authors":"V. K. Kalyanam, E. Mahurin, K. Bowman, J. Abraham","doi":"10.1109/CICC48029.2020.9075933","DOIUrl":null,"url":null,"abstract":"A randomized pulse-modulation (RPM) circuit controls the instruction-issue rate in a Qualcomm® Hexagon™ compute DSP (CDSP) for adapting performance to limit current and temperature below target thresholds. The current and temperature limiting system contains on-die current and temperature sensors, a limits evaluation (LE) circuit, and the RPM instruction-issue control circuit. When current or temperature exceeds a target threshold, the RPM instruction-issue control circuit adjusts performance in ~5 CDSP clock cycles after accounting for the clock-domain-crossing synchronization overhead to satisfy the 1µs latency requirement for the entire limiting system. Silicon measurements from a 7nm Hexagon™ CDSP demonstrate that the RPM instruction-issue control circuit enables a 0.4% performance resolution across a wide range of operation from 100% to 0.4% while avoiding thread starvation during multi-threaded execution to maintain quality of service.","PeriodicalId":409525,"journal":{"name":"2020 IEEE Custom Integrated Circuits Conference (CICC)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Randomized Pulse-Modulating Instruction-Issue Control Circuit for a Current and Temperature Limiting System in a 7nm Hexagon™ Compute DSP\",\"authors\":\"V. K. Kalyanam, E. Mahurin, K. Bowman, J. Abraham\",\"doi\":\"10.1109/CICC48029.2020.9075933\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A randomized pulse-modulation (RPM) circuit controls the instruction-issue rate in a Qualcomm® Hexagon™ compute DSP (CDSP) for adapting performance to limit current and temperature below target thresholds. The current and temperature limiting system contains on-die current and temperature sensors, a limits evaluation (LE) circuit, and the RPM instruction-issue control circuit. When current or temperature exceeds a target threshold, the RPM instruction-issue control circuit adjusts performance in ~5 CDSP clock cycles after accounting for the clock-domain-crossing synchronization overhead to satisfy the 1µs latency requirement for the entire limiting system. Silicon measurements from a 7nm Hexagon™ CDSP demonstrate that the RPM instruction-issue control circuit enables a 0.4% performance resolution across a wide range of operation from 100% to 0.4% while avoiding thread starvation during multi-threaded execution to maintain quality of service.\",\"PeriodicalId\":409525,\"journal\":{\"name\":\"2020 IEEE Custom Integrated Circuits Conference (CICC)\",\"volume\":\"45 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2020-03-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2020 IEEE Custom Integrated Circuits Conference (CICC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CICC48029.2020.9075933\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 IEEE Custom Integrated Circuits Conference (CICC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC48029.2020.9075933","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Randomized Pulse-Modulating Instruction-Issue Control Circuit for a Current and Temperature Limiting System in a 7nm Hexagon™ Compute DSP
A randomized pulse-modulation (RPM) circuit controls the instruction-issue rate in a Qualcomm® Hexagon™ compute DSP (CDSP) for adapting performance to limit current and temperature below target thresholds. The current and temperature limiting system contains on-die current and temperature sensors, a limits evaluation (LE) circuit, and the RPM instruction-issue control circuit. When current or temperature exceeds a target threshold, the RPM instruction-issue control circuit adjusts performance in ~5 CDSP clock cycles after accounting for the clock-domain-crossing synchronization overhead to satisfy the 1µs latency requirement for the entire limiting system. Silicon measurements from a 7nm Hexagon™ CDSP demonstrate that the RPM instruction-issue control circuit enables a 0.4% performance resolution across a wide range of operation from 100% to 0.4% while avoiding thread starvation during multi-threaded execution to maintain quality of service.