采用并行处理架构的VDPCM硬件实现

Conference Proceeding IEEE Pacific Rim Conference on Communications, Computers and Signal Processing Pub Date : 1989-06-01 DOI:10.1109/PACRIM.1989.48446

K. Thyagarajan

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引用次数: 1

摘要

描述了实现实时图像编码应用的VDPCM编码器/解码器硬件的并行处理架构。该架构由模块化形式的处理元素组成，每个模块都是围绕AT&T的DSP32芯片设计的。该系统具有灵活性和可扩展性。利用该硬件对图像进行了0.5 bit像素的编码，并给出了编码结果。硬件结果与计算机模拟结果一致

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Hardware implementation of a VDPCM using parallel processing architecture

A parallel processing architecture is described to implement the VDPCM encoder/decoder hardware for real-time image coding applications. The architecture consists of processing elements in modular form, and each module is designed around AT&T's DSP32 chip. The system is flexible and expandable. The hardware was used to encode images at a rate of 0.5 bit pixel, and results are given. The hardware results are in agreement with the computer simulations.<>

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Conference Proceeding IEEE Pacific Rim Conference on Communications, Computers and Signal Processing

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