利用动态可重构fpga增强系统可靠性

K. Kwiat, W. Debany, S. Hariri
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引用次数: 0

摘要

配置计算模块进行容错或并行计算时,需要具备一定的逻辑功能。这些功能的硬件和软件实现之间不可避免的权衡为设计创造了不利的属性。软件中的分支和跳转只允许立即需要的功能占用处理资源,但是软件无法与专用硬件中执行功能的速度相匹配。然而,硬件是刚性的,并且在其中永久包含功能会增加系统的开销(尺寸、重量和功率)。简化硬件以减少这种开销只会限制在操作期间如何配置模块。我们的架构使用动态可重构现场可编程门阵列(FPGA),将硬件和软件的优点结合在一起,同时降低两者的成本。在提高应用吞吐量的同时,灵活、明智地支持计算模块间的容错和多处理。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Enhancing system dependability with dynamically reconfigurable FPGAs
Configuring computing modules for fault-tolerant or parallel computing requires the presence of certain logical functions. Unavoidable tradeoffs between hardware and software implementations of these functions have created unfavorable attributes for designs. Branching and jumps in software allow only the immediately needed function to take up processing resources, but software cannot match the speed of performing the function in dedicated hardware. Hardware, however, is rigid, and permanently embodying functions in it adds to the overhead (size, weight and power) of the system. Simplifying the hardware to reduce this overhead only restricts how the modules can be configured during operation. Our architecture uses a dynamically reconfigurable field-programmable gate array (FPGA) to bring together the benefits of hardware and software while mitigating the costs of both. The resultant design supports fault tolerance and multiprocessing among computing modules flexibly and judiciously while accelerating the application throughput.
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