采用赛灵思射频SoC的直接转换数字波束形成阵列接收器,在28ghz下具有800mhz信道带宽

S. Pulipati, V. Ariyarathna, Udara De Silva, Najath Akram, E. Alwan, A. Madanayake, S. Mandal, T. Rappaport
{"title":"采用赛灵思射频SoC的直接转换数字波束形成阵列接收器,在28ghz下具有800mhz信道带宽","authors":"S. Pulipati, V. Ariyarathna, Udara De Silva, Najath Akram, E. Alwan, A. Madanayake, S. Mandal, T. Rappaport","doi":"10.1109/COMCAS44984.2019.8958039","DOIUrl":null,"url":null,"abstract":"This paper discusses early results associated with a fully-digital direct-conversion array receiver at 28 GHz. The proposed receiver makes use of commercial off-the-shelf (COTS) electronics, including the receiver chain. The design consists of a custom 28 GHz patch antenna sub-array providing gain in the elevation plane, with azimuthal plane beamforming provided by real-time digital signal processing (DSP) algorithms running on a Xilinx Radio Frequency System on Chip (RF SoC). The proposed array receiver employs element-wise fully-digital array processing that supports ADC sample rates up to 2 GS/second and up to 1 GHz of operating bandwidth per antenna. The RF mixed-signal data conversion circuits and DSP algorithms operate on a single-chip RFSoC solution installed on the Xilinx ZCU1275 prototyping platform.","PeriodicalId":276613,"journal":{"name":"2019 IEEE International Conference on Microwaves, Antennas, Communications and Electronic Systems (COMCAS)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"17","resultStr":"{\"title\":\"A Direct-Conversion Digital Beamforming Array Receiver with 800 MHz Channel Bandwidth at 28 GHz using Xilinx RF SoC\",\"authors\":\"S. Pulipati, V. Ariyarathna, Udara De Silva, Najath Akram, E. Alwan, A. Madanayake, S. Mandal, T. Rappaport\",\"doi\":\"10.1109/COMCAS44984.2019.8958039\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper discusses early results associated with a fully-digital direct-conversion array receiver at 28 GHz. The proposed receiver makes use of commercial off-the-shelf (COTS) electronics, including the receiver chain. The design consists of a custom 28 GHz patch antenna sub-array providing gain in the elevation plane, with azimuthal plane beamforming provided by real-time digital signal processing (DSP) algorithms running on a Xilinx Radio Frequency System on Chip (RF SoC). The proposed array receiver employs element-wise fully-digital array processing that supports ADC sample rates up to 2 GS/second and up to 1 GHz of operating bandwidth per antenna. The RF mixed-signal data conversion circuits and DSP algorithms operate on a single-chip RFSoC solution installed on the Xilinx ZCU1275 prototyping platform.\",\"PeriodicalId\":276613,\"journal\":{\"name\":\"2019 IEEE International Conference on Microwaves, Antennas, Communications and Electronic Systems (COMCAS)\",\"volume\":\"49 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"17\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 IEEE International Conference on Microwaves, Antennas, Communications and Electronic Systems (COMCAS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/COMCAS44984.2019.8958039\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 IEEE International Conference on Microwaves, Antennas, Communications and Electronic Systems (COMCAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/COMCAS44984.2019.8958039","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 17

摘要

本文讨论了28ghz全数字直接转换阵列接收机的早期结果。所提出的接收器使用商用现货(COTS)电子设备,包括接收器链。该设计包括一个定制的28 GHz贴片天线子阵列,在仰角面提供增益,在方位面波束形成由运行在Xilinx射频系统芯片(RF SoC)上的实时数字信号处理(DSP)算法提供。所提出的阵列接收器采用单元全数字阵列处理,支持ADC采样率高达2 GS/秒,每个天线的工作带宽高达1 GHz。RF混合信号数据转换电路和DSP算法在安装在Xilinx ZCU1275原型平台上的单芯片RFSoC解决方案上运行。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A Direct-Conversion Digital Beamforming Array Receiver with 800 MHz Channel Bandwidth at 28 GHz using Xilinx RF SoC
This paper discusses early results associated with a fully-digital direct-conversion array receiver at 28 GHz. The proposed receiver makes use of commercial off-the-shelf (COTS) electronics, including the receiver chain. The design consists of a custom 28 GHz patch antenna sub-array providing gain in the elevation plane, with azimuthal plane beamforming provided by real-time digital signal processing (DSP) algorithms running on a Xilinx Radio Frequency System on Chip (RF SoC). The proposed array receiver employs element-wise fully-digital array processing that supports ADC sample rates up to 2 GS/second and up to 1 GHz of operating bandwidth per antenna. The RF mixed-signal data conversion circuits and DSP algorithms operate on a single-chip RFSoC solution installed on the Xilinx ZCU1275 prototyping platform.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:604180095
Book学术官方微信