{"title":"60 GHz 200mb /s 10mw超再生接收机","authors":"K. Liang, Luis Chen, C. Yue","doi":"10.1109/VDAT.2009.5158158","DOIUrl":null,"url":null,"abstract":"This paper presents a low-power and high-speed super-regenerative receiver operating at the 60-GHz using 65-nm CMOS technology. The receiver uses the simplicity and power efficiency architecture for short-range communication. The proposed receiver achieves a data rate of 200 Mb/s with current consumption of 10 mA at a supply voltage of 1 V. The corresponding energy consumption of 50 pJ per receiver bit was an excellent tradeoff between cost, performance and power consumption.","PeriodicalId":246670,"journal":{"name":"2009 International Symposium on VLSI Design, Automation and Test","volume":"7 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"A 200-Mb/s 10-mW super-regenerative receiver at 60 GHz\",\"authors\":\"K. Liang, Luis Chen, C. Yue\",\"doi\":\"10.1109/VDAT.2009.5158158\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a low-power and high-speed super-regenerative receiver operating at the 60-GHz using 65-nm CMOS technology. The receiver uses the simplicity and power efficiency architecture for short-range communication. The proposed receiver achieves a data rate of 200 Mb/s with current consumption of 10 mA at a supply voltage of 1 V. The corresponding energy consumption of 50 pJ per receiver bit was an excellent tradeoff between cost, performance and power consumption.\",\"PeriodicalId\":246670,\"journal\":{\"name\":\"2009 International Symposium on VLSI Design, Automation and Test\",\"volume\":\"7 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-04-28\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 International Symposium on VLSI Design, Automation and Test\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VDAT.2009.5158158\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 International Symposium on VLSI Design, Automation and Test","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VDAT.2009.5158158","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 200-Mb/s 10-mW super-regenerative receiver at 60 GHz
This paper presents a low-power and high-speed super-regenerative receiver operating at the 60-GHz using 65-nm CMOS technology. The receiver uses the simplicity and power efficiency architecture for short-range communication. The proposed receiver achieves a data rate of 200 Mb/s with current consumption of 10 mA at a supply voltage of 1 V. The corresponding energy consumption of 50 pJ per receiver bit was an excellent tradeoff between cost, performance and power consumption.
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