多千兆协议AES的高效高吞吐量FPGA实现

Ulfat Hussain, H. Jamal
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引用次数: 23

摘要

由于加密信道对高吞吐量架构的要求,需要一种高效的硬件实现。这可以通过使用高端可重构平台的智能利用来实现。为了实现令人信服的高吞吐量,提出了一种在现场可编程门阵列(FPGA)上实现多千兆协议的128位密钥高级加密标准(AES)的高效非流水线方式。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
An Efficient High Throughput FPGA Implementation of AES for Multi-gigabit Protocols
Due to the requirement of high throughput architecture for encrypted channels, an efficient implementation of hardware is needed. This can be achieved by using smart utilization of high end reconfigurable platforms. To achieve convincingly high throughput, an efficient non-pipelined style implementation of Advanced Encryption Standard (AES) with key size of 128-bit, for multigigabit protocols on Field Programmable Gate Array (FPGA)is presented.
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