{"title":"256 QAM调制解调器全数字自适应均衡器的设计","authors":"M. Bolla, L. Rossi, A. Spalvieri, A. D'andrea","doi":"10.1109/ICC.1988.13773","DOIUrl":null,"url":null,"abstract":"A theoretical study of the performance and development of an equalizer that complies with the stringent specifications imposed by a 256 QAM, 2*40 Mb/s system (rate=35 Msymbol/s) is presented. Design rules for the accuracy of the internal arithmetic and A/D converters are suggested. The analysis is based on the following main parameters: (1) dynamic ranges, (2) step size and accumulator length, (3) effect of digital quantizing, and (4) arithmetic design of the correlators. An accurate theory of operation is presented with examples of simulation results.<<ETX>>","PeriodicalId":191242,"journal":{"name":"IEEE International Conference on Communications, - Spanning the Universe.","volume":"19 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1988-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Design of a fully digital adaptive equalizer for a 256 QAM modem\",\"authors\":\"M. Bolla, L. Rossi, A. Spalvieri, A. D'andrea\",\"doi\":\"10.1109/ICC.1988.13773\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A theoretical study of the performance and development of an equalizer that complies with the stringent specifications imposed by a 256 QAM, 2*40 Mb/s system (rate=35 Msymbol/s) is presented. Design rules for the accuracy of the internal arithmetic and A/D converters are suggested. The analysis is based on the following main parameters: (1) dynamic ranges, (2) step size and accumulator length, (3) effect of digital quantizing, and (4) arithmetic design of the correlators. An accurate theory of operation is presented with examples of simulation results.<<ETX>>\",\"PeriodicalId\":191242,\"journal\":{\"name\":\"IEEE International Conference on Communications, - Spanning the Universe.\",\"volume\":\"19 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1988-06-12\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE International Conference on Communications, - Spanning the Universe.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICC.1988.13773\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE International Conference on Communications, - Spanning the Universe.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICC.1988.13773","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design of a fully digital adaptive equalizer for a 256 QAM modem
A theoretical study of the performance and development of an equalizer that complies with the stringent specifications imposed by a 256 QAM, 2*40 Mb/s system (rate=35 Msymbol/s) is presented. Design rules for the accuracy of the internal arithmetic and A/D converters are suggested. The analysis is based on the following main parameters: (1) dynamic ranges, (2) step size and accumulator length, (3) effect of digital quantizing, and (4) arithmetic design of the correlators. An accurate theory of operation is presented with examples of simulation results.<>
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