{"title":"1992 VHDL标准化概述","authors":"M. Shahdad","doi":"10.1109/EURDAC.1992.246197","DOIUrl":null,"url":null,"abstract":"The author reports on the VHSIC hardware description language (VHDL) standardization process. A brief description is given of language design objectives, areas of language change, language documentation, language validation, modeling, simulation, synthesis and upward compatibility.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"52 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"1992 VHDL standardization overview\",\"authors\":\"M. Shahdad\",\"doi\":\"10.1109/EURDAC.1992.246197\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The author reports on the VHSIC hardware description language (VHDL) standardization process. A brief description is given of language design objectives, areas of language change, language documentation, language validation, modeling, simulation, synthesis and upward compatibility.<<ETX>>\",\"PeriodicalId\":218056,\"journal\":{\"name\":\"Proceedings EURO-DAC '92: European Design Automation Conference\",\"volume\":\"52 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1992-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings EURO-DAC '92: European Design Automation Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EURDAC.1992.246197\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings EURO-DAC '92: European Design Automation Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EURDAC.1992.246197","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
The author reports on the VHSIC hardware description language (VHDL) standardization process. A brief description is given of language design objectives, areas of language change, language documentation, language validation, modeling, simulation, synthesis and upward compatibility.<>
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