{"title":"用于芯片上大规模并行系统的位串行浮点单元","authors":"M. Schimmler, B. Schmidt, Hans-Werner Lang","doi":"10.1080/10637190410001725454","DOIUrl":null,"url":null,"abstract":"This paper presents the design of a new bit-serial floating-point unit (FPU). It has been developed for the processors of the instruction systolic array (ISA) parallel computer model. In contrast to conventional bit-parallel FPUs the bit-serial approach requires a different data format. Our FPU uses an IEEE compliant internal floating-point format that allows a fast least significant bit (LSB)-first arithmetic and can be efficiently implemented in hardware. Tel.:+49-431-880-4480. Fax:+49-431-880-4054masch@informatik.uni-kiel.de Tel.:+49-461-8051235. Fax:+49-461-8051527lang@fh-flensburg.de","PeriodicalId":406098,"journal":{"name":"Parallel Algorithms and Applications","volume":"14 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A bit-serial floating-point unit for a massively parallel system on a chip\",\"authors\":\"M. Schimmler, B. Schmidt, Hans-Werner Lang\",\"doi\":\"10.1080/10637190410001725454\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents the design of a new bit-serial floating-point unit (FPU). It has been developed for the processors of the instruction systolic array (ISA) parallel computer model. In contrast to conventional bit-parallel FPUs the bit-serial approach requires a different data format. Our FPU uses an IEEE compliant internal floating-point format that allows a fast least significant bit (LSB)-first arithmetic and can be efficiently implemented in hardware. Tel.:+49-431-880-4480. Fax:+49-431-880-4054masch@informatik.uni-kiel.de Tel.:+49-461-8051235. Fax:+49-461-8051527lang@fh-flensburg.de\",\"PeriodicalId\":406098,\"journal\":{\"name\":\"Parallel Algorithms and Applications\",\"volume\":\"14 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-06-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Parallel Algorithms and Applications\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1080/10637190410001725454\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Parallel Algorithms and Applications","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1080/10637190410001725454","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A bit-serial floating-point unit for a massively parallel system on a chip
This paper presents the design of a new bit-serial floating-point unit (FPU). It has been developed for the processors of the instruction systolic array (ISA) parallel computer model. In contrast to conventional bit-parallel FPUs the bit-serial approach requires a different data format. Our FPU uses an IEEE compliant internal floating-point format that allows a fast least significant bit (LSB)-first arithmetic and can be efficiently implemented in hardware. Tel.:+49-431-880-4480. Fax:+49-431-880-4054masch@informatik.uni-kiel.de Tel.:+49-461-8051235. Fax:+49-461-8051527lang@fh-flensburg.de
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
