Conductance Enhancement of C-shaped Graphene Nanoribbon Circuit Interconnect through Defect Treatment

We investigate the enhancement of the conductance of a dual bend (C-shaped) graphene interconnect by introducing various defect patterns. For certain defect patterns, an increase in conductance is observed. The defect pattern is optimized to a double atomic irregular defect pattern. It is important to note that implantation of the proposed defect pattern in the C-shaped interconnect results in a conductance of 1 e2/h at zero energy value, which is almost insensitive to a change in interconnect width. This study can aid in the realization of compact and efficient 2D electronic circuits, paving the way for modern VLSI Design and Embedded System.