Y. Boulghassoul, P. Adell, J. Rowe, L. Massengill, peixiong zhao, A. Sternberg
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System-level design hardening based on worst-case ASET simulations
We present experimental and simulation results on single-event transients in an analog subsystem for satellite electronic equipment. Investigations based on worst-case transient events, simulated with transistor-level circuit models, suggest design modifications for hardening.