用于SDH设备时钟的数字锁相环路

ICMMT 2000. 2000 2nd International Conference on Microwave and Millimeter Wave Technology Proceedings (Cat. No.00EX364) Pub Date : 2000-09-14 DOI:10.1109/ICMMT.2000.895664

Shi Guowei, Wang Qing, Chen Ming

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摘要

本文介绍了用于SDH设备时钟(SEC)的高稳定数字锁相环的设计原理，并报告了本实验室的主要测试结果。测试结果表明，该数字锁相环具有良好的参考频率跟踪性能。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A digital phase locked loop used in SDH equipment clock

The paper introduces the design principle of a highly stable digital phase locked loop used in an SDH equipment clock (SEC), and the chief test results obtained in our lab are reported. The test results show that the digital phase locked loop has the excellent performance to track the reference frequency.

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ICMMT 2000. 2000 2nd International Conference on Microwave and Millimeter Wave Technology Proceedings (Cat. No.00EX364)

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