高可制造STT-MRAM嵌入28nm逻辑的演示

Y. Song, J. Lee, Sung-hee Han, H. Shin, K. H. Lee, K. Suh, D. Jeong, G. Koh, Sechung Oh, Joon-Min Park, Soojeoung Park, B. Bae, O. I. Kwon, K. Hwang, Bum-seok Seo, You Kyoung Lee, S. Hwang, Dongsoo Lee, Y. Ji, Kyu-Charn Park, G. Jeong, Hyunju Hong, K. Lee, H. K. Kang, E. Jung
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引用次数: 64

摘要

通过实现稳定的功能和强大的封装级可靠性,我们成功地展示了嵌入28nm FDSOI逻辑平台的8Mb STT-MRAM的可制造性。利用先进的MTJ堆叠技术和图像化技术,通过提高TMR值和减小单元电阻分布,大大提高了读取余量。采用新颖的集成工艺,提高了效率,提高了写保证金。通过HTOL 1000小时测试、106次耐久测试、保持性测试,在封装层面确认了产品的可靠性。为了更广泛的应用,我们还演示了高密度128Mb STT-MRAM的可行性。基于这些结果,我们清楚地验证了嵌入式STT-MRAM的产品可制造性。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Demonstration of Highly Manufacturable STT-MRAM Embedded in 28nm Logic
We successfully demonstrated the manufacturability of 8Mb STT-MRAM embedded in 28nm FDSOI logic platform by achieving stable functionality and robust package level reliability. Read margin were greatly improved by increasing TMR value and also reducing distribution of cell resistance using advanced MTJ stack and patterning technology. Write margin was also increased by improving the efficiency using novel integration process. Its product reliability was confirmed in package level with passing HTOL 1000 hours tests, 106 endurance test, and retention test. For a wider application, we also demonstrated the feasibility of high density 128Mb STT-MRAM. Based on these results, we clearly verified the product manufacturability of embedded STT-MRAM.
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