Analysis and design of amplitude error detector and digital control loop to increase reliability of PLL

A digital control loop scheme for a high speed PLL is suggested to detect amplitude errors at the output of the oscillator. Reliability specifications of the PLL are likely to be violated in case of excessive output swing in the oscillators. In addition, low amplitude swings will have negative influences on the phase noise of LC oscillators. As a result, the performance and reliability of the PLL will be reduced. The design includes a novel amplitude error detector. The amplitude error detector generates a digital word to show the situation of the amplitude error. The structure is implemented in 65nm CMOS technology. The power consumption of one amplitude error detector from 1V power supply is 0.76mW.