{"title":"16位CORDIC的完整自定义数据路径","authors":"Zhuo Bi, Yijun Dai","doi":"10.1109/ICACI.2012.6463320","DOIUrl":null,"url":null,"abstract":"A radix-2 16 bits CORDIC (CoOrdinate Rotation DIgital Computer) architecture which includes pipelined and parallelism is presented in this paper. A full custom technology for CORDIC datapath which is used in the proposed architecture for 16-bit precision can improve the throughout and decrease the area. As a result, the silicon area of the data-path is 11699.877μm2 in the 45nm CMOS technology library and the critical path delay is 875ps at the SS (Slow-Slow) corners whose Voltage and Temperature are 1.1V and 75° respectively. Based on the layout level, the simulation results show that the design has characteristics of high speed and small area in full custom technology.","PeriodicalId":404759,"journal":{"name":"2012 IEEE Fifth International Conference on Advanced Computational Intelligence (ICACI)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Full custom datapath of 16-bit CORDIC\",\"authors\":\"Zhuo Bi, Yijun Dai\",\"doi\":\"10.1109/ICACI.2012.6463320\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A radix-2 16 bits CORDIC (CoOrdinate Rotation DIgital Computer) architecture which includes pipelined and parallelism is presented in this paper. A full custom technology for CORDIC datapath which is used in the proposed architecture for 16-bit precision can improve the throughout and decrease the area. As a result, the silicon area of the data-path is 11699.877μm2 in the 45nm CMOS technology library and the critical path delay is 875ps at the SS (Slow-Slow) corners whose Voltage and Temperature are 1.1V and 75° respectively. Based on the layout level, the simulation results show that the design has characteristics of high speed and small area in full custom technology.\",\"PeriodicalId\":404759,\"journal\":{\"name\":\"2012 IEEE Fifth International Conference on Advanced Computational Intelligence (ICACI)\",\"volume\":\"16 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2012-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2012 IEEE Fifth International Conference on Advanced Computational Intelligence (ICACI)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICACI.2012.6463320\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 IEEE Fifth International Conference on Advanced Computational Intelligence (ICACI)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICACI.2012.6463320","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A radix-2 16 bits CORDIC (CoOrdinate Rotation DIgital Computer) architecture which includes pipelined and parallelism is presented in this paper. A full custom technology for CORDIC datapath which is used in the proposed architecture for 16-bit precision can improve the throughout and decrease the area. As a result, the silicon area of the data-path is 11699.877μm2 in the 45nm CMOS technology library and the critical path delay is 875ps at the SS (Slow-Slow) corners whose Voltage and Temperature are 1.1V and 75° respectively. Based on the layout level, the simulation results show that the design has characteristics of high speed and small area in full custom technology.