Projecting Performance for PIUMA using Down-Scaled Simulation

Programmable Integrated Unified Memory Architecture (PIUMA) is Intel's novel graph analysis optimized processor architecture, targeted at efficiently executing graph algorithms on very large graphs. Simulation is used to project its performance for various algorithms before the system is built. However, simulators are limited in the number of cores and threads they can simulate, because of their low simulation speed, high resource usage and poor scalability. Therefore, it is practically impossible to simulate PIUMA at its full system scale. In this paper, we present downscaled simulation, a technique to project performance of a large scale system using a small scale simulation. We apply the technique to PIUMA, showing how to configure the downscaled system in order to accurately reflect the characteristics of the full system. We evaluate downscaled simulation on a set of graph applications, showing that it accurately tracks simulation results of small scale simulations, as well as the projections to large systems made by an analytical model.