FPGA-based embedded Logic Controllers

In general case, reconfigurable logic controllers (RLC) are included into reactive digital embedded systems, carrying out control for several processes proceeding concurrently. The paper presents a practical application of a formal, rule-based specification language in Gentzen sequent logic, which is used as an intermediate textual description of a control interpreted Petri net. On the other hand exactly the same description serves also as logic design expressions, related with different versions of functionally equivalent concurrent state machine models, considered on Register Transfer Level. The symbolic rule-based specification of Petri net-based embedded Logic Controllers (LCs) can be step-by step formally transformed into the final specification of concurrent state machine model, closely related with VHDL description, suitable for a direct mapping in reconfigurable logic devices. In this paper it is proposed novel compact form of logic descriptions, directly based on event-oriented specification, where it is assumed that macrocells can be implicitly formed by synthesis tool as containing virtual T flip-flops.