{"title":"并行容错计算结构","authors":"Z. Segall, M. Yoeli, E. Strasbourger","doi":"10.1049/IJ-CDT:19790018","DOIUrl":null,"url":null,"abstract":"A parallel fault-tolerant computation structure (p.f.t.n.) is introduced, consisting of a control structure and a device structure. The control structure (c.f.n.) models parallel-system synchronisation and graceful degradation by reconfiguration after fault occurrence. The device structure models the parallel data flow. Liveness conditions of a c.f.n. are discussed, and a relationship between liveness and net configuration is developed and proved.","PeriodicalId":344610,"journal":{"name":"Iee Journal on Computers and Digital Techniques","volume":"35 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1979-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Parallel fault-tolerant computation structure\",\"authors\":\"Z. Segall, M. Yoeli, E. Strasbourger\",\"doi\":\"10.1049/IJ-CDT:19790018\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A parallel fault-tolerant computation structure (p.f.t.n.) is introduced, consisting of a control structure and a device structure. The control structure (c.f.n.) models parallel-system synchronisation and graceful degradation by reconfiguration after fault occurrence. The device structure models the parallel data flow. Liveness conditions of a c.f.n. are discussed, and a relationship between liveness and net configuration is developed and proved.\",\"PeriodicalId\":344610,\"journal\":{\"name\":\"Iee Journal on Computers and Digital Techniques\",\"volume\":\"35 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1979-04-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Iee Journal on Computers and Digital Techniques\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1049/IJ-CDT:19790018\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Iee Journal on Computers and Digital Techniques","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1049/IJ-CDT:19790018","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A parallel fault-tolerant computation structure (p.f.t.n.) is introduced, consisting of a control structure and a device structure. The control structure (c.f.n.) models parallel-system synchronisation and graceful degradation by reconfiguration after fault occurrence. The device structure models the parallel data flow. Liveness conditions of a c.f.n. are discussed, and a relationship between liveness and net configuration is developed and proved.
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