{"title":"90纳米CMOS MMIC放大器","authors":"M. A. Masud, H. Zirath, M. Ferndahl, H. Vickes","doi":"10.1109/RFIC.2004.1320570","DOIUrl":null,"url":null,"abstract":"Small signal amplifiers at 20 and 40 GHz, based on a 90 nm CMOS process are demonstrated. A gain of 5.8 dB at 20 GHz for single stage has been obtained with a 1 dB compression point at 1 dBm. The corresponding figures for the 40 GHz amplifiers are 6 dB and -5.75 dBm. Noise figure for the 20 GHz amplifier is 6.4 dB. Both single gate access and double gate access transistors have been used in the design. DC power consumption of the 20 GHz single stage amplifier was found to be 10 mW whereas for the 40 GHz double stage amplifier it is approximately 19 mW. Total circuit area is 0.7/spl times/0.8 mm/sup 2/ for the single stage and 1/spl times/0.7 mm/sup 2/ for the 40 GHz double stage amplifier.","PeriodicalId":140604,"journal":{"name":"2004 IEE Radio Frequency Integrated Circuits (RFIC) Systems. Digest of Papers","volume":"3 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"78","resultStr":"{\"title\":\"90 nm CMOS MMIC amplifier\",\"authors\":\"M. A. Masud, H. Zirath, M. Ferndahl, H. Vickes\",\"doi\":\"10.1109/RFIC.2004.1320570\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Small signal amplifiers at 20 and 40 GHz, based on a 90 nm CMOS process are demonstrated. A gain of 5.8 dB at 20 GHz for single stage has been obtained with a 1 dB compression point at 1 dBm. The corresponding figures for the 40 GHz amplifiers are 6 dB and -5.75 dBm. Noise figure for the 20 GHz amplifier is 6.4 dB. Both single gate access and double gate access transistors have been used in the design. DC power consumption of the 20 GHz single stage amplifier was found to be 10 mW whereas for the 40 GHz double stage amplifier it is approximately 19 mW. Total circuit area is 0.7/spl times/0.8 mm/sup 2/ for the single stage and 1/spl times/0.7 mm/sup 2/ for the 40 GHz double stage amplifier.\",\"PeriodicalId\":140604,\"journal\":{\"name\":\"2004 IEE Radio Frequency Integrated Circuits (RFIC) Systems. Digest of Papers\",\"volume\":\"3 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-06-06\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"78\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2004 IEE Radio Frequency Integrated Circuits (RFIC) Systems. Digest of Papers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/RFIC.2004.1320570\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2004 IEE Radio Frequency Integrated Circuits (RFIC) Systems. Digest of Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RFIC.2004.1320570","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Small signal amplifiers at 20 and 40 GHz, based on a 90 nm CMOS process are demonstrated. A gain of 5.8 dB at 20 GHz for single stage has been obtained with a 1 dB compression point at 1 dBm. The corresponding figures for the 40 GHz amplifiers are 6 dB and -5.75 dBm. Noise figure for the 20 GHz amplifier is 6.4 dB. Both single gate access and double gate access transistors have been used in the design. DC power consumption of the 20 GHz single stage amplifier was found to be 10 mW whereas for the 40 GHz double stage amplifier it is approximately 19 mW. Total circuit area is 0.7/spl times/0.8 mm/sup 2/ for the single stage and 1/spl times/0.7 mm/sup 2/ for the 40 GHz double stage amplifier.
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