{"title":"用于带内全双工通信的100nm GaAs工艺ka波段前端","authors":"Talat Cetin, C. Onol, G. Selcuk","doi":"10.1109/EUROCON.2019.8861560","DOIUrl":null,"url":null,"abstract":"In this study the authors introduce a Ka-band front-end to be used for in-band full-duplex (IBFD) communications. The design consists of a Rat-Race coupler to provide self-interference cancellation (SIC), a low noise amplifier (LNA), a power amplifier (PA) and an electrical balancing impedance; all implemented in 100nm low noise GaAs process provided by UMS. The circuit provided an isolation above 40 dB between the PA and the LNA. The 1 dB compression point of the transmitter at the antenna terminal is 12 dBm and the total noise Figure (NF) is better than 5 dB. The balancing impedance covers 3:1 voltage standing wave ratio (VSWR) circle in Smith chart. The chip consumes 500 mW power and has a die area of 7mm2.","PeriodicalId":232097,"journal":{"name":"IEEE EUROCON 2019 -18th International Conference on Smart Technologies","volume":"6 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A Ka-Band Front-End in 100nm GaAs Process for In-Band Full Duplex Communications\",\"authors\":\"Talat Cetin, C. Onol, G. Selcuk\",\"doi\":\"10.1109/EUROCON.2019.8861560\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this study the authors introduce a Ka-band front-end to be used for in-band full-duplex (IBFD) communications. The design consists of a Rat-Race coupler to provide self-interference cancellation (SIC), a low noise amplifier (LNA), a power amplifier (PA) and an electrical balancing impedance; all implemented in 100nm low noise GaAs process provided by UMS. The circuit provided an isolation above 40 dB between the PA and the LNA. The 1 dB compression point of the transmitter at the antenna terminal is 12 dBm and the total noise Figure (NF) is better than 5 dB. The balancing impedance covers 3:1 voltage standing wave ratio (VSWR) circle in Smith chart. The chip consumes 500 mW power and has a die area of 7mm2.\",\"PeriodicalId\":232097,\"journal\":{\"name\":\"IEEE EUROCON 2019 -18th International Conference on Smart Technologies\",\"volume\":\"6 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-07-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE EUROCON 2019 -18th International Conference on Smart Technologies\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EUROCON.2019.8861560\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE EUROCON 2019 -18th International Conference on Smart Technologies","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EUROCON.2019.8861560","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A Ka-Band Front-End in 100nm GaAs Process for In-Band Full Duplex Communications
In this study the authors introduce a Ka-band front-end to be used for in-band full-duplex (IBFD) communications. The design consists of a Rat-Race coupler to provide self-interference cancellation (SIC), a low noise amplifier (LNA), a power amplifier (PA) and an electrical balancing impedance; all implemented in 100nm low noise GaAs process provided by UMS. The circuit provided an isolation above 40 dB between the PA and the LNA. The 1 dB compression point of the transmitter at the antenna terminal is 12 dBm and the total noise Figure (NF) is better than 5 dB. The balancing impedance covers 3:1 voltage standing wave ratio (VSWR) circle in Smith chart. The chip consumes 500 mW power and has a die area of 7mm2.
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