用于集成电路/大规模集成电路电磁兼容特性建模和测量的功率去耦电路

R. Koga, O. Wada, Y. Toyota, T. Miyashita, Y. Fukumoto, A. Namba, Y. Takahata, N. Kagawa
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引用次数: 1

摘要

提出了一种将集成电路与外围电源电路解耦的电路结构。在电磁干扰驱动功率的标准测量和印刷电路板的低电磁干扰电路设计上都有突出的优点。两级解耦电路是有效的。这些讨论现在是在集总电路基础上进行的,应该进一步扩展到分布参数系统,因为电磁系统本质上是分布的,考虑到实际电子应用,要考虑的上限频率实际上是开放的。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Power decoupling circuit for modeling and measurement of EMC characteristics of IC/LSI
A circuit configuration is proposed which decouples an IC from the peripheral power source circuit. Merit is extended both on the standard measurement of the the EMI driving power and also on the low EMI circuit design of printed circuit boards. The two-stage decoupling circuit is found effective. These discussions are now conducted on a lumped circuit base, which should be further extended to distributed-parameter systems because the electromagnetic system is intrinsically distributed and the limit of the upper frequency to be considered is actually open referring to actual electronics applications.
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