芯片多处理器中可扩展的邻近感知缓存复制

2011 International Conference on Parallel Architectures and Compilation Techniques Pub Date : 2011-10-10 DOI:10.1109/PACT.2011.35

Chongmin Li, Haixia Wang, Y. Xue, Dongsheng Wang, Jian Li

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引用次数: 0

摘要

我们提出了就近感知缓存复制(PAR)，这是一种LLC复制技术，它将智能缓存复制放置机制和基于分层目录的一致性协议优雅地集成到一个具有成本效益和可扩展的设计中。在64核CMP上的仿真结果表明，在SPLASH2和PARSEC工作负载下，PAR可以比基线共享缓存设计实现12%的加速。它还提供了大约5%的加速，比一些现代的方法更简单和可扩展的支持。

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Scalable Proximity-Aware Cache Replication in Chip Multiprocessors

We propose Proximity-Aware cache Replication (PAR), an LLC replication technique that elegantly integrates an intelligent cache replication placement mechanism and a hierarchical directory-based coherence protocol into one cost-effective and scalable design. Simulation results on a 64-core CMP show that PAR can achieve 12\% speedup over the baseline shared cache design with SPLASH2 and PARSEC workloads. It also provides around 5\% speedup over a couple contemporary approaches with much simpler and scalable support.

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2011 International Conference on Parallel Architectures and Compilation Techniques

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