一种单片48v - 1v 10A四倍降压DC-DC变换器，具有迟滞复制准时4相控制和2倍摆率全迟滞模式

2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2022-06-12 DOI:10.1109/vlsitechnologyandcir46769.2022.9830233

Hyunki Han, Min-Woo Ko, Jeong-Hyun Cho, Gyeong-Gu Kang, Seok-Tae Koh, H. Bae, Hyunsik Kim

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引用次数: 3

摘要

本文介绍了一种48v - 1v四次降压(QSD) DC-DC变换器。QSD由4个并联电感和3个串联电容组成，通过降低开关电压四分之一，可以有效地为全单片12V LDMOS提供高达10A的电源。滞回复制准时(HCOT)控制允许4相QSD无时钟同步，而不会崩溃串联电容器电压。在极端负载波动情况下，还提出了两相全滞后(2x摆率)模式来缓解电压下降。在0.18 μm BCD中制备的芯片，在6.3A/50ns负载转换时，效率峰值为88.5%，sag为∆80mV，恢复时间为1μs。

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A Monolithic 48V-to-1V 10A Quadruple Step-Down DC-DC Converter with Hysteretic Copied On-Time 4-Phase Control and 2× Slew Rate All-Hysteretic Mode

This paper presents a 48V-to-1V quadruple step-down (QSD) DC-DC converter. The QSD comprising 4 parallel-inductors and 3 series-capacitors can efficiently supply up to 10A with fully monolithic 12V LDMOS by lowering the switching voltage to be quartered. The hysteretic copied on-time (HCOT) control allows clockless synchronization of 4-phase QSD without collapsing series-capacitor voltages. The 2-phase all-hysteretic (2× slew rate) mode is also presented for voltage droop mitigation under extreme load fluctuations. The chip fabricated in 0.18-μm BCD shows a peak efficiency of 88.5% and achieves ∆80mV sag and 1μs 2%-recovery time for a 6.3A/50ns load transition.

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2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)

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