Programmable PLL-based frequency synthesizer: Modeling and design considerations

This work summarizes the set of building and operating features for a third-order Charge Pump Phase-Locked Loop CP-PLL-based Frequency Synthesizer for clock generation. For implementation purpose, a derived architectural solution for N integer frequency division is proposed considering the particular design requirements in the PLL programmability. Additionally, from the set of reference design equations, a derived set of models are proposed for Low Pass Filter LPF design, considering the voltage controlled oscillator VCO input capacitance effects. From the PLL settings at simulation environment, circuit level results indicate a settling time TS < 2 μs, considering the divide ratio N variation (8–16).