Shigeya Tanaka, T. Hotta, F. Murabayashi, H. Yamada, Shoji Yoshida, K. Shimamura, K. Katsura, T. Bandoh, Koichi Ikeda, Kenji Matsubara, Kouji Saitou, T. Nakano, Teruhisa Shimizu, R. Satomura
{"title":"120mhz BiCMOS超标量RISC处理器","authors":"Shigeya Tanaka, T. Hotta, F. Murabayashi, H. Yamada, Shoji Yoshida, K. Shimamura, K. Katsura, T. Bandoh, Koichi Ikeda, Kenji Matsubara, Kouji Saitou, T. Nakano, Teruhisa Shimizu, R. Satomura","doi":"10.1109/VLSIC.1993.920514","DOIUrl":null,"url":null,"abstract":"Several techniques such as BiCMOS, RISC, and superscalar have been developed to increase microprocessor performance. In the superscalar processor, multiple instructions should be fetched from the instruction cache and issued to the execution unit every machine cycle. However, due to the complex logic that is necessary for multiple issuing of instructions, the resulting machine cycle time tends to be relatively long. Consequently, the tradeoffs between clock rate and superscalar complexity should be carefully examined. In this paper, we describe a superscalar RISC processor which attains high operation speed.","PeriodicalId":127467,"journal":{"name":"Symposium 1993 on VLSI Circuits","volume":"36 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1993-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":"{\"title\":\"A 120 MHz BiCMOS superscalar RISC processor\",\"authors\":\"Shigeya Tanaka, T. Hotta, F. Murabayashi, H. Yamada, Shoji Yoshida, K. Shimamura, K. Katsura, T. Bandoh, Koichi Ikeda, Kenji Matsubara, Kouji Saitou, T. Nakano, Teruhisa Shimizu, R. Satomura\",\"doi\":\"10.1109/VLSIC.1993.920514\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Several techniques such as BiCMOS, RISC, and superscalar have been developed to increase microprocessor performance. In the superscalar processor, multiple instructions should be fetched from the instruction cache and issued to the execution unit every machine cycle. However, due to the complex logic that is necessary for multiple issuing of instructions, the resulting machine cycle time tends to be relatively long. Consequently, the tradeoffs between clock rate and superscalar complexity should be carefully examined. In this paper, we describe a superscalar RISC processor which attains high operation speed.\",\"PeriodicalId\":127467,\"journal\":{\"name\":\"Symposium 1993 on VLSI Circuits\",\"volume\":\"36 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1993-05-19\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"10\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Symposium 1993 on VLSI Circuits\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.1993.920514\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Symposium 1993 on VLSI Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.1993.920514","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Several techniques such as BiCMOS, RISC, and superscalar have been developed to increase microprocessor performance. In the superscalar processor, multiple instructions should be fetched from the instruction cache and issued to the execution unit every machine cycle. However, due to the complex logic that is necessary for multiple issuing of instructions, the resulting machine cycle time tends to be relatively long. Consequently, the tradeoffs between clock rate and superscalar complexity should be carefully examined. In this paper, we describe a superscalar RISC processor which attains high operation speed.
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