基于CORDIC的快速广义voronoi图硬件加速器用于机器人的高效探索

Yi Zhan, Zihao Wang, Jiarui Xu, Guoyi Yu, F. An, Wenzheng Chi, Chao Wang
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引用次数: 0

摘要

提出了一种基于快速收敛坐标旋转数字计算机(CORDIC)的广义Voronoi图(GVD)硬件加速器,用于高效的机器人路径探索。由于快速收敛的CORDIC所带来的高精度,与基线设计相比,所提出的GVD硬件加速器显著提高了探索路径的精度。更高的探测精度使得机器人的轨迹更短,从而进一步降低了整个机器人系统的功耗。因此,我们的设计适用于电池供电的小型机器人。FPGA实现表明,该设计在12位定点工作时,探索路径的精度比基线设计提高了54%,机器人系统功耗比基线设计降低了20%。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Fast CORDIC based Generalized-Voronoi-Diagram Hardware Accelerator for Efficient Robotic Exploration
This paper proposes a fast-convergence CO-ordinate Rotation DIgital Computer (CORDIC) based Generalized Voronoi Diagram (GVD) hardware accelerator for efficient robotic path exploration. Owing to the high precision contributed by fast-convergence CORDIC, the proposed GVD hardware accelerator significantly improves the accuracy of the explored paths as compared to the baseline design. Higher precision of the exploration causes shorter trajectory of the robot, which further reduces the power consumption of the entire robot system. Therefore, our design is suitable to the battery-powered small-scale robots. FPGA implementation shows that, the proposed design operating at 12-bit fixed point achieves 54% higher precision of the explored paths and 20% lower power consumption of the robot system than the baseline design, respectively.
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