BGA封装采用绝缘线减少模具面积

Shailesh Kumar, Vikas Garg, C. Verma, Rishi Bhooshan, Poh Zi-Song, L. C. Tan
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引用次数: 0

摘要

在传统的线键合封装中,设计规则要求单个键合线不能相互接触。此外,处理粘合单元可能会引起导线扰动,导致导线短路。如图1所示,绝缘导线键合技术通过在键合导线上涂覆一层不导电层,消除了这一要求,因此,即使在导线相互物理接触后,也能保持电隔离[1-2]。本文的重点是利用绝缘线键合技术在提高电气参数和减少模具尺寸方面的模具设计实施效率。本文讨论了两种具体实现方法。一种是实现片外去耦电容,用它来代替保证信号完整性所需的片上电容,节省宝贵的硅面积。第二种实现是实现网格型电网,改善IR下降,同时摆脱多个电源/接地垫,从而节省硅面积。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
BGA packaging using insulated wire for die area reduction
In conventional wire bonded packages, design rules require that individual bond wires not touch each other. Also, handling of bonded units may cause wire disturbance leading to wire short. Insulated wire bonding techniques eliminate this requirement by coating a non conductive layer over the bond wires as shown in Fig.1 and thus, electrical isolation is maintained even after wires physically touch each other [1-2]. The focus of this paper is to leverage the insulated wire-bonding technology for die design implementation efficiency in terms of improving electrical parameters and die size reduction. Two specific implementation are discussed in this paper. One is to implement off-chip decoupling capacitor and use it to replace on-die capacitors required for signal integrity and save precious silicon area. Second implementation is about realizing mesh type power grid to improve the IR drop and simultaneously get rid of multiple Power/Ground pads and thus, save silicon area.
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