Hot Row Identification of DRAM Memory in a Multicore System

Access locality in single-core system is not easily observed in multicore system due to interleaved requests from different cores. Requests that come to DRAM-based main memory is mapped to a specific bank in DRAM and accessed through row buffer in the bank. DRAM row-buffer conflicts occur when a sequence of requests on different rows goes to the same memory bank, causing much higher memory access latency than requests to the same row or to different banks. In this paper, we first show that strong locality exists in memory requests of multicore systems. For many workloads, the accesses to some rows are more frequent than others, which we call them hot rows. Based on the observation, we propose a simple hot row buffer (HRB) scheme that is able to detect and capture these hot rows in DRAM. Results have shown that the proposed scheme is able to provide average 56% hit ratio over all row accesses in a bank for 10 selected workloads from SPEC CPU2006. A simple stream prefetcher prefetching in the hot row is implemented and results show an average of 9.1% IPC improvement over no prefetcher design.